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¸Þ¸ð¸® IC A290021UL-70
½Î´Ù!! 2Mbit Ç÷¡½¬¸Þ¸ð¸®, 256Kbit x 8,
ÆÇ¸Å°¡°Ý : 2,160¿ø
Àû¸³±Ý :22¿ø
»óǰ»óÅ :½Å»óǰ
Á¦Ç°ÄÚµå :1056720
Á¦Á¶»ç :AMIC
Ãâ½ÃÀÏ :2018-02-07
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MCUÀÌ¿ë ²ÜÆÁ

2,280¿ø
4,200¿ø
4,560¿ø
1,620¿ø
4,560¿ø
4,560¿ø
5,760¿ø
1,800¿ø
4,200¿ø
34,500¿ø
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A290021UL-70

FEATURES

  • 5.0V ¡¾ 10% for read and write operations
  • Access times:
    - 55/70/90/120/150 (max.)
  • Current:
    - 20 mA typical active read current
    - 30 mA typical program/erase current
    - 1 mA typical CMOS standby
  • Flexible sector architecture
    - 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX3 sectors
    - Any combination of sectors can be erased
    - Supports full chip erase
    - Sector protection:
    A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector
  • Top or bottom boot block configurations available
  • Embedded Erase Algorithms
    - Embedded Erase algorithm will automatically erase the entire chip or any combination of designated
    sectors and verify the erased sectors
    - Embedded Program algorithm automatically writes and verifies bytes at specified addresses
  • Typical 100,000 program/erase cycles per sector
  • 20-year data retention at 125¡ÆC
    - Reliable operation for the life of the system
  • Compatible with JEDEC-standards
    - Pinout and software compatible with single-powersupply Flash memory standard
    - Superior inadvertent write protection
  • Data Polling and toggle bits
    - Provides a software method of detecting completion of program or erase operations
  • Erase Suspend/Erase Resume
    - Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation
  • Hardware reset pin (RESET )
    - Hardware method to reset the device to reading array data (not available on A290021)
  • Package options
    - 32-pin P-DIP, PLCC, or TSOP (Forward type)

 

Ordering Information

  • Package : 32Pin PLCC

 




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