A290021UL-70 | | 
| FEATURES | |
| - 5.0V ± 10% for read and write operations
- Access times:
- 55/70/90/120/150 (max.)
- Current:
- 20 mA typical active read current
- 30 mA typical program/erase current
- 1 mA typical CMOS standby
- Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX3 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector
- Top or bottom boot block configurations available
- Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase the entire chip or any combination of designated
sectors and verify the erased sectors
- Embedded Program algorithm automatically writes and verifies bytes at specified addresses - Typical 100,000 program/erase cycles per sector
- 20-year data retention at 125°C
- Reliable operation for the life of the system
- Compatible with JEDEC-standards
- Pinout and software compatible with single-powersupply Flash memory standard
- Superior inadvertent write protection
- Data Polling and toggle bits
- Provides a software method of detecting completion of program or erase operations
- Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation
- Hardware reset pin (RESET )
- Hardware method to reset the device to reading array data (not available on A290021)
- Package options
- 32-pin P-DIP, PLCC, or TSOP (Forward type)
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| Ordering Information | |
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통신판매업신고번호 제2011-인천남구-0460호 개인정보관리자 박정웅 
MCU이용 
