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통신IC TSB41AB2
IEEE1394용 PHY칩, 1394버스를 구성하실려면 이것이 필요하죠. IEEE 1394a-2000 TWO-PORT CABLE Transceiver/Arbiter, 64-Pin TQFP
판매가격 : 4,200
적립금 :42
상품상태 :신상품
제품코드 :5743
제조사 :TI
출시일 :2018-02-07
구매수량 :
총 금액 :
MCU이용 꿀팁

720원
3,840원
840원
10,200원
11,760원
6,720원
1,080원
2,440원
3,000원
12,960원
상세정보 배송/취소/교환안내 이용후기 상품Q&A

TSB41AB2

Features

  • Fully Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus† and IEEE 1394a-2000
  • Fully Interoperable With FireWireTMand i.LINKTMImplementation of IEEE Std 1394
  • Fully Compliant With OpenHCI Requirements
  • Provides Two IEEE 1394a-2000 Fully Compliant Cable Ports at 100/200/400 Megabits Per Second (Mbits/s)
  • Full IEEE 1394a-2000 Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-By Concatenation, Port Disable/Suspend/Resume
  • Register Bits Give Software Control of Contender Bit, Power Class Bits, Link Active Control Bit and IEEE 1394a-2000 Features
  • IEEE 1394a-2000 Compliant Common Mode Noise Filter on Incoming TPBIAS
  • Extended Resume Signaling for Compatibility With Legacy DV Devices, and Terminal- and Register-Compatibility With TSB41LV02A, Allow Direct Isochronous Transmit to Legacy DV Devices With Any Link Layer Even When Root
  • Power-Down Features to Conserve Energy in Battery Powered Applications Include: Automatic Device Power Down During Suspend, Device Power-Down Terminal, Link Interface Disable via LPS, and Inactive Ports Powered Down
  • Fail-Safe Circuitry Senses Sudden Loss of Power to the Device and Disables the Port to Ensure That the Device Does Not Load TPBIAS of the Connected Device and Blocks Any Leakage Path From the Port Back to the Device Power Plane
  • Software Device Reset (SWR)
  • Industry Leading Low Power Consumption
  • Ultralow-Power Sleep Mode
  • Cable Power Presence Monitoring
  • Cable Ports Monitor Line Conditions for Active Connection to Remote Node
  • Data Interface to Link Layer Controller Through 2/4/8 Parallel Lines at 49.152 MHz
  • Interface to Link Layer Controller Supports Low-Cost TI Bus-Holder Isolation and Optional Annex J Electrical Isolation
  • Interoperable With Link Layer Controllers Using 3.3 V
  • Single 3.3-V Supply Operation
  • Low-Cost 24.576-MHz Crystal Provides Transmit, Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz
  • Low-Cost High-Performance 64-Pin TQFP Thermally Enhanced PowerPADTMPackage Increases Thermal Performance by up to 210%
  • Meets IntelTM Mobile Power Guideline 2000

 

Ordering Information

  • Package : 64pin TQFP


TSB41AB2.pdf 1

 

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